Two-phase Logic Design by Hardware Flowcharts

The need for two-phase logic design is driven by marketing requirements to provide the most silicon efficient implementation of digital VLSI circuits. This has led to an industry wide development of more area efficient techniques that represent a departure from the traditional edgetriggered state machine methodology. In the past these techniques have been largely adhoc. However, we have developed a rigorous approach to designing two-phase digital sequential logic that is based on using high level flowcharts. The incentive for designing logic by flowcharting is the same as the reason for designing software by flowcharting. It is more complete and less prone to error because ideas are formulated at a higher level. At this higher level, a larger perspective is easier to achieve, thus making potential conceptual problems easier to detect. In addition, the ability of humans to solve problems by visual pattern recognition allows hardware flowcharting to facilitate the design process, as opposed to just providing a communication link between the designer and the computer. While not as well known as flowcharting techniques used for developing computer software, flowchart methods have been used in the past for hardware development. Trednnick [Tre81] described a “flowchart method” for designing the central processing unit (CPU) of a computer system. The Trednnick flowcharting methodology is targeted for system level applications rather than IC design. Another example of a hardware flowcharting technique is the Daisy Computer Systems Hardware Compiler [Dai86]. The Hardware Compiler is a set of software programs that converts a high level logic flowchart into a truth table. The limitation of the Hardware Compiler “flowchart” procedure is that it can be applied only to single phase or edge-triggered designs. While there has been other, more recent, interest in high level graphical design, support for structured two-phase logic has not been addressed. We have created a design environment based on flowcharts[Yam93]. The front end is an editor for entering and modifying flowcharts. The editor can write out a textual description of the flowchart which in turn can be directly translated to a high level description language such as VHDL or Verilog HDL. This HDL can be used as the input for commercially available synthesis tools. Since the flowchart is high level and structured, the design is synthesized in a desirable and predictable manner, allowing less experienced engineers to take full advantage of logic synthesis without first learning the idiosyncrasies of a particular HDL. In addition to using the HDL as input to synthesis tools, we have developed a path to HSIS, a formal verification tool from UC Berkeley. HSIS will allow us to formally prove properties of our two-phase designs, such as the relative ordering of events. This will allow us to reduce the effort of functional verification currently done by logic simulation. The organization of the paper is as follows: Section 2 contains a brief description of structured two-phase Abstract